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xilinx-suite

Coding & development

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Updated 10-15 22:09

About this skill

Xilinx Full Toolchain Skill

This skill helps you complete the full Xilinx (AMD) design flow, generating scripts and files that can run directly.

Step 1: Determine the tool and flow

When receiving any Xilinx-related request, first determine which stage the user is in, then load the corresponding reference file.

Complete Design Flow Overview

[可选] Vitis HLS        →    Vivado          →    Vitis Unified / PetaLinux
C/C++ 算法 → IP 核        硬件平台设计           软件开发 / Linux 系统
  hls_guide.md              vivado_guide.md      vitis_unified_guide.md
                          + mpsoc_ps_config.md    petalinux_guide.md
                          + xdc_constraints.md

Tool Routing Table

Task Described by User Required Tool Reference File to Load
C/C++ algorithm acceleration, pragma optimization, generate IP Vitis HLS ../../references/hls_guide.md
Create project, Block Design, configure PS/IP, XDC, bitstream Vivado ../../references/vivado_guide.md + load on demand
Detailed PS configuration (DDR, MIO, clocks) Vivado ../../references/mpsoc_ps_config.md
IO pin constraints, timing constraints Vivado ../../references/xdc_constraints.md
JESD204B→C migration, high-speed serial ADC/DAC interfaces Vivado ../../references/jesd204b_to_c_migration.md
Embedded software, bare-metal programs, RTOS, platform/domain Vitis Unified ../../references/vitis_unified_guide.md
Embedded Linux, kernel configuration, rootfs, boot images PetaLinux ../../references/petalinux_guide.md
Run gRPC C++ server / Python client on PetaLinux, ZMQ→gRPC migration, expose RPC via udmabuf+AXI DMA PetaLinux ../../references/grpc_on_petalinux.md
Find official document numbers, UG/PG/DS number lookup, document purpose explanation General ../../references/official-docs/index.md

Step 2: Requirements Confirmation (Must Be Done First)

Before generating any script, confirm the following information (actively ask questions for items without clear answers):

Required confirmation for all projects

  1. Target device/development board: full part number or board model (provided by the user)
  2. Vivado/Vitis version(e.g. 2023.2, 2024.1)
  3. Design objective: what function should this project implement?

Additional confirmation for HLS projects

  1. Algorithm description: inputs, outputs and functionality of the C/C++ function
  2. Performance targets: target clock frequency, latency, throughput requirements
  3. Interface type: AXI4-Lite (control), AXI4-Stream (data), AXI4-Master (memory access)

Additional confirmation for Vivado projects (MPSoC type)

  1. PS configuration: DDR type and capacity, MIO peripherals (UART, Ethernet, USB, SD, etc.)
  2. PL IP requirements: which AXI IPs are needed, whether there are custom HDL modules
  3. Clock requirements: PL clock frequency (pl0_ref_clk)

Additional confirmation for Vitis projects

  1. Runtime environment: bare metal (standalone), FreeRTOS, or Linux userspace
  2. Processor core：A53、R5、MicroBlaze
  3. XSA file path: hardware description file exported from Vivado

Additional confirmation for PetaLinux projects

  1. BSP or XSA: is there a vendor BSP? Or use the XSA exported directly from Vivado?
  2. Custom requirements: whether drivers/applications/device tree overlays need to be added

Step 3: Execute according to the tool flow

After confirming the requirements, load the corresponding reference files and generate the script step by step.

Timing for loading reference files

Always read the reference files before generating the script, do not generate Tcl/XSCT/commands from memory, because the APIs differ across Vivado/Vitis versions.

Vivado 工程  → 先读 ../../references/vivado_guide.md
              → 如有 PS  → 再读 ../../references/mpsoc_ps_config.md
              → 如有 IO  → 再读 ../../references/xdc_constraints.md
              → 如有 JESD204 → 再读 ../../references/jesd204b_to_c_migration.md

HLS 工程     → 先读 ../../references/hls_guide.md

Vitis 工程   → 先读 ../../references/vitis_unified_guide.md

PetaLinux    → 先读 ../../references/petalinux_guide.md
              → 如需 gRPC（C++ server / Python client、ZMQ 迁移）→ 再读 ../../references/grpc_on_petalinux.md

Output specifications

Each time a script is generated, you must provide:

  1. A complete, runnable script file（.tcl、.xdc、.py, shell scripts, etc.)
  2. Run command: How to execute it on the command line or in the GUI
  3. Expected output: Which files will be produced after the script runs successfully
  4. Next-step hints: What should be done after completing this stage

File organization specifications

project_root/
├── 01_hls/                  ← Vitis HLS 工程（可选）
│   ├── hls_create.tcl
│   └── src/*.cpp / *.h
│
├── 02_vivado/               ← Vivado 硬件工程
│   ├── create_project.tcl
│   ├── create_bd.tcl
│   ├── add_sources.tcl
│   ├── constraints/design.xdc
│   ├── build.tcl
│   └── output/
│       ├── design.bit
│       └── design_fixed.xsa
│
├── 03_vitis/                ← Vitis 软件工程
│   ├── create_platform.tcl  (XSCT 脚本)
│   ├── create_app.tcl
│   └── src/*.c / *.h
│
└── 04_petalinux/            ← PetaLinux（可选）
    ├── build.sh
    └── config/

Cross-tool data flow

Vitis HLS                    Vivado                    Vitis / PetaLinux
─────────────────────────────────────────────────────────────────────────
hls_ip/                  →   IP Catalog
  solution/impl/ip       →   (add_files / ip_repo)
                             ↓
                         project.xsa         →        平台/BSP/Linux BSP
                         design.bit          →        boot/BOOT.BIN

Common errors and precautions

  1. Version compatibility: Vivado 2022.x+ write_hw_platform replaces the older write_sysdef; the Tcl API of Vitis Unified 2022.x+ differs significantly from the Classic version
  2. XSA type：write_hw_platform(pre-synthesis, editable) vs write_hw_platform -fixed -include_bit(post-implementation, fixed and containing the bitstream)
  3. Importing HLS IP into Vivado: You need to add the HLS IP repository path in the Vivado project and refresh the IP catalog
  4. PetaLinux version matching: The PetaLinux version must match the Vivado version (for example, both use 2023.2)
  5. Device family determination：zu starting with → MPSoC;vu/ku/xc7 → pure FPGA;xcvc → Versal

Reference files

  • ../../references/vivado_guide.md: Vivado project creation, Block Design, synthesis and implementation, report analysis
  • ../../references/mpsoc_ps_config.md: Detailed Zynq UltraScale+ PS configuration (DDR, MIO, clock parameters)
  • ../../references/xdc_constraints.md: Complete XDC constraints guide (timing, IO, exception constraints)
  • ../../references/hls_guide.md: Vitis HLS project flow (C/C++ → IP)
  • ../../references/vitis_unified_guide.md: Vitis Unified IDE 2022.x+ project flow
  • ../../references/petalinux_guide.md: PetaLinux system build flow
  • ../../references/jesd204b_to_c_migration.md: JESD204B→C IP migration guide (port mapping, data bit width, AXI registers, common pitfalls)
  • ../../references/grpc_on_petalinux.md: PetaLinux + gRPC end-to-end deployment guide (rootfs configuration, libutf8_range symlink, VM pre-generated .pb.cc + on-board g++, udmabuf/AXI DMA RPC exposure, ZMQ→gRPC migration, common pitfalls such as RCU stall)
  • ../../references/official-docs/index.md: Xilinx/AMD official documentation index (UG/PG/DS/XAPP numbers, titles, purposes, and their correspondence to the reference guides in this repository)