crg-req-to-design

CRG Requirement → Design Table Generator

Convert the CRG requirements table(subsystem, IP, clock/reset signal names, notes/frequency) automatically into a clock tree design table and a reset tree design table, and recommend the number of PLLs and the clock tree architecture.

The generated design tables can be used directly as input for cr_tree_diag_gen , forming a complete pipeline:

需求表 → crg_req_to_design → 设计表 → cr_tree_diag_gen → drawio / excalidraw

Capabilities

• Requirements table parsing: supports Excel (.xlsx/.xls) and CSV, with fuzzy column name matching (bilingual Chinese-English)
• Automatic frequency extraction: recognizes from notes formats such as 200MHz、3Mhz、20/25MHz , and automatically normalizes to MHz
• Automatic signal classification: automatically distinguishes clocks from resets based on suffixes (_clk、_rst_n , etc.)
• Pad input identification: identifies external clock sources based on signal names (pad、xtal、osc) or notes ("external"/"input")
• PLL count recommendation: based on integer division relationships, prioritizes using pad clocks to derive internal clocks; when derivation is not possible, recommends PLLs by frequency clustering
• Clock tree architecture generation: automatically infers SRC0、DIV、DIV_WIDTH、DIV_DFLT, and generates a clock tree design table conforming to the cr_tree_diag_gen format
• Default reset tree generation: uses PORESETn as the root, and automatically generates output nodes for all subsystem reset signals
• Architecture report output: a text report summarizing the recommended PLLs, division chains, and reset tree structure

Input Format (Requirements Table)

Column Name	Alias	Description
Subsystem	subsystem, module, block	The subsystem it belongs to (supports Excel merged cells)
IP	ip, module name	The IP it belongs to (optional)
Clock/reset requirements	signal, signal name, name, clock/reset	Signal name (e.g., core_clk）
Notes	note, frequency, freq, remark, comment	Frequency, description, etc. (e.g., 200MHz）

Output Files

After running, 3 files will be generated in the output directory:

File	Description
clock_design.xlsx	Clock tree design table (compatible with cr_tree_diag_gen）
reset_design.xlsx	Reset tree design table (compatible with cr_tree_diag_gen）
crg_report.txt	PLL recommendation and clock tree architecture report

How to Use

Command line

# 基本用法
python scripts/main.py <req_table.xlsx> [output_dir]

# 示例
python scripts/main.py examples/input/req_table.xlsx output/

MCP Server

In .kimi/mcp.json , add:

{
  "mcpServers": {
    "crg-req-to-design": {
      "command": "python3",
      "args": ["/path/to/crg_req_to_design/mcp_server.py"]
    }
  }
}

Exposed tools：

Tool	Function
crg_req_to_design	Requirements table → clock design table + reset design table + architecture report

Call parameters：

{
  "input_path": "/path/to/req_table.xlsx",
  "output_dir": "/path/to/output"
}

Returns the list of generated files, PLL recommendations, and a division chain summary.

Integration with cr_tree_diag_gen

# 1. 生成设计表
python crg_req_to_design/scripts/main.py req_table.xlsx output/

# 2. 生成时钟树拓扑图
python cr_tree_diag_gen/scripts/main.py output/clock_design.xlsx clock_tree.drawio

# 3. 生成复位树拓扑图
python cr_tree_diag_gen/scripts/main.py output/reset_design.xlsx reset_tree.drawio

Design Principles

• Table-driven: the Excel requirements table is the only input; changing the requirements changes the architecture
• Minimum PLL principle: prioritizes using existing pad clocks or integer division relationships of PLLs to reduce the number of PLLs
• Editable intermediate artifacts: the generated design tables are kept as Excel, so users can manually fine-tune details such as SRC, DIV, and MUX before feeding them into the drawing tool
• Zero intrusion: pure Python, no dependency on EDA tools

Dependencies

Running this skill independently only requires:

pip install pandas openpyxl

If the MCP Server is enabled, it also requires:

pip install mcp

Agent call chain

This skill is only responsible forthe first half: requirements table → design table + report.

If you need to generate a visual topology diagram (.drawio / .excalidraw），you need to call cr_tree_diag_gen skill to process the generated design table.

需求表
  ↓
【crg_req_to_design】  →  clock_design.xlsx + reset_design.xlsx + crg_report.txt
                              ↓
                  【cr_tree_diag_gen】  →  .drawio / .excalidraw

Call order：

1. First call crg_req_to_design, passing in the requirements table path
2. obtain from the output directory the clock_design.xlsx and reset_design.xlsx
3. then call cr_tree_diag_gen, using the above design table as input, to generate the topology diagram

Format compatibility：crg_req_to_design The column names, order, and format of the design table generated by cr_tree_diag_gen are completely consistent with the input standard of , and can be passed directly without manual adjustment.

Algorithm Details

PLL recommendation logic

1. For each internal clock, iterate through all pad clocks and look for an integer division ratio div ∈ [1, 64]
2. If |pad_freq / div - tgt_freq| / tgt_freq ≤ 5%, consider that this clock can be obtained by dividing the pad
3. If it cannot be obtained from a pad, try to obtain it by dividing an already created PLL (high-frequency PLLs first)
4. If it still cannot be obtained, create a new PLL for that frequency; clocks with the same frequency share this PLL

Reset tree logic

• PORESETn(or the first reset signal) as the input root node
• nTRST、nSRST Debug resets such as as independent input
• Resets of other subsystems as output，SRC0 = PORESETn

Notes

1. Multi-frequency pad: a note such as "20/25MHz" will extract the first frequency as the primary frequency; the complete string is retained in the NOTE column for manual editing
2. Clock without frequency: if a clock has no frequency marked, no PLL will be created for it, SRC0 will be left blank, and the user must specify it manually
3. ICG/OCC: the requirements table usually does not contain gating/scan information; the ICG/OCC columns in the design table are left blank and the user can supplement them later
4. Same pad name distinction: of different subsystems pad_clk will be treated as independent input nodes; if merging is needed, please use a unified name in the requirements table or merge manually in the design table