SuperAPI AI Directory

cr-tree-diag-gen

Design & creation

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Updated 10-16 08:46

About this skill

CR Tree Diagram Generator

Clock/reset tree link diagram generator. Converts Excel tables into topology diagrams in Draw.io or Excalidraw format.

Capabilities

  • Clock tree visualization: Generates a complete link diagram from an Excel clock table (Source → MUX → DIV → OCC → ICG → Output)
  • Reset tree visualization: Generates a reset link diagram from an Excel reset table (including SOFT/REG/AND nodes)
  • Dual-format output: Generates both .drawio(diagrams.net) and .excalidraw(excalidraw.com)
  • Smart layout: Arranged from top to bottom in the original table order, with intermediate nodes dynamically distributed according to link length
  • MUX support: SRC0/SRC1 dual-input MUX nodes, with dynamically calculated level
  • Edge coloring: Edges from different source clocks use different colors (red/blue/green, etc.)
  • Frequency annotation: NOTE column content (e.g., 1000MHz) is automatically displayed inside the node box
  • Orthogonal routing: Draw.io supports jump arcs, Excalidraw supports vertical-then-horizontal routing

When to Use

When the user needs to:

  • Draw a clock tree / draw a reset tree / draw a clock link diagram
  • Convert an Excel clock table into a topology diagram
  • Generate drawio / excalidraw clock diagrams
  • Visualize CRG / clock distribution / reset distribution
  • Check clock sources and frequency division relationships

Input Format

Clock Tree table (Clock Tree)

Column name Description Example
NAME Signal name core_clk
ATTR Attribute: input/internal/output/na output
SRC0 Parent clock 0 (main source) pll_mux_clk
SRC1 Parent clock 1 (MUX second input) pad_src_clk
MUX_DFLT MUX default value 0
DIV Divider 2
DIV_WIDTH Divider bit width 4
DIV_DFLT Divider default value 1
OCC OCC control Y
ICG ICG control Y
ICG_DFLT ICG default value 1
NOTE Comment/frequency 1000MHz

Reset Tree table (Reset Tree)

Column name Description Example
NAME Signal name core_rst_n
ATTR Attribute: input/internal/output output
SRC0 Parent reset 0 por_rst_n
SRC1~SRC3 Additional input (AND gate) soft_rst_n
SOFT_DFLT Software default value 1

How to Use

Command line

# 同时生成 drawio + excalidraw
python3 cr_tree_diag_gen/main.py input.xlsx

# 指定输出路径(只生成一种格式)
python3 cr_tree_diag_gen/main.py input.xlsx output.drawio
python3 cr_tree_diag_gen/main.py input.xlsx output.excalidraw

MCP Tool

Generated directly via the cr_tree_diag_gen tool:

{
  "input_path": "/path/to/clock_table.xlsx",
  "output_dir": "/path/to/output"
}

Returns the list of generated files.

Output

File How to open
*_tree.drawio https://app.diagrams.net
*_tree.excalidraw https://excalidraw.com(直接拖入)

Node Types & Colors

Type Color Description
source_input Green #27ae60 External input clock
source_internal Gray #7f8c8d Internally generated clock
na Orange #f39c12 Intermediate node (non-output)
output Light blue #aed6f1 Final output clock
div White #ffffff Divider
occ Purple #f5eef8 Clock gating controller
icg Green #d5f5e3 Clock gating
mux Purple #e8daef Multiplexer
rst_and Yellow #fff3bf Reset AND gate
reg Blue #d6eaf8 Register node
soft Orange #fdebd0 Software control node

Design Principles

  • Zero intrusion: Pure Python script, no dependency on draw.io / excalidraw installation
  • Table-driven: Excel is the only input; modifying the table modifies the diagram
  • Automatic inference: When no output path is specified, the filename is inferred automatically, and both formats are generated at the same time
  • Backward compatible: The NOTE column is optional; generation is unaffected when there is no NOTE

Dependencies

pip install pandas openpyxl

MCP Server

Quick configuration

In .kimi/mcp.json add:

{
  "mcpServers": {
    "cr-tree-diag-gen": {
      "command": "python3",
      "args": ["/path/to/cr_tree_diag_gen/mcp_server.py"]
    }
  }
}

Exposed tools

Tool Features
cr_tree_diag_gen xlsx → drawio + excalidraw
cr_tree_diag_gen_drawio xlsx → drawio only
cr_tree_diag_gen_excalidraw xlsx → excalidraw only

Notes

  1. Automatically detect table type: Has SOFT_DFLT column → reset tree, otherwise → clock tree
  2. Intermediate nodes: DIV/OCC/ICG are automatically created based on table columns and do not need to be defined separately
  3. Isolated source filtering: Input nodes such as test_mode / clk_gen_rst_n with no outgoing edges are automatically hidden
  4. Excalidraw limitations: arc jumpers are not supported; trapezoidal MUX is rendered as a rectangle