external-gitcode-ascend-triton-operator-design

Triton Operator Requirement Document Generation

Workflow

1. Requirement Analysis → Output: function definition, mathematical formula, competitor comparison
2. Prototype Design → Output: API interface definition
3. Specification Constraints → Output: input/output constraints, hardware limitations
4. Feature Implementation → Output: tiling strategy, kernel implementation plan

Reference Resource Loading

Stage	Must Load	Do Not Load
Requirement Analysis	ascend-terminology.md	template, tiling-strategies
Prototype Design	triton-api-reference.md	tiling-strategies
Feature Implementation	tiling-strategies.md, triton-operator-template.md	ascend-terminology

MANDATORY: Before Stage 4, fully read tiling-strategies.md and triton-operator-template.md, with no line limit. Output the document in the template format.

Key Terms

• GM: Global Memory (DDR),UB: Vector Core high-speed cache (192KB),L1: Cube Core cache (~1MB)
• AI Core: A2/A3 has 24, including 1 Cube + 2 Vector
• Reduction operations must be upcast to FP32

Things to Absolutely Never Do

• ❌ Use vague terms ("appropriate partitioning", "reasonable allocation") — specific calculation methods must be given
• ❌ Ignore UB size (192KB) and alignment requirements (32B)
• ❌ Do not distinguish Vector Core (vector computation) and Cube Core (matrix computation)
• ❌ Do not annotate data types and GM↔UB transfers in dataflow diagrams
• ❌ Do not specify the upcast strategy for reduction operations

Common Pitfalls

Pitfall	Symptom	Solution
UB overflow	Plan is not implementable	Total compute buffer size < 192KB
Memory not aligned	Hardware error	UB buffers 32B aligned, single-value buffers allocated 32B
Precision loss	FP16 results inaccurate	Upcast to FP32 before reduction, downcast after completion
Unreasonable tiling	Poor performance/large shapes unsupported	Partition by dimension, avoid cross-Core data dependencies