external-cannbot-ops-triton-op-designer

Triton Ascend Algorithm Sketch Design Skill

Your task is to design a high-quality algorithm sketch based on the following fixed configuration:

• Target DSL: triton_ascend
• Target Framework: torch
• Target Backend: ascend
• Target Architecture: {{ arch }}

⚠️ Youonly generate algorithm sketches, and do not generate executable code. Sketches are used to guide subsequent code generation (triton-op-coding).

Input Information

You will receive the following information:

1. Task description and specification — operator requirements in operator task format (including the Model category)
2. Relevant knowledge and examples — UnifiedSketch DSL specification and design patterns (see knowledge loading rules below)
3. Execution history — previous design feedback and optimization suggestions (during iterative design)

Knowledge Loading Rules

Required knowledge (loaded for every design)

• @references/sketch-design.md — UnifiedSketch DSL syntax specification, core operations, design patterns, best practices

• Hardware specifications Detailed hardware specification reference: @../npu-arch/references/npu-arch-guide-triton.md and @../npu-arch/references/npu-hardware-params.md

  Use the read tool to read the hardware specification file for the corresponding architecture.

Handwritten optimization cases (select the 2 most relevant based on the task)

Based on the operator type in the task description, select from the following cases the2 most relevantto load. Selection criteria: operator type match > data scale closeness > optimization pattern similarity.

Category	Case File	Core Optimization
Elementwise	@references/cases/elemwise-broadcast-2d.md	2D broadcast: do not split the small dimension, load outside the loop
	@references/cases/elemwise-broadcast-3d.md	Cross-axis 3D broadcast: two-stage kernel
	@references/cases/elemwise-cast.md	int8→fp16: secondary splitting + fully utilize UB
	@references/cases/elemwise-concat.md	Slice+Concat fusion: precise slice load
	@references/cases/elemwise-zeros.md	Small shape: fewer cores, reduced scheduling overhead
Index	@references/cases/index-histogram.md	Histogram: pre-sort + binary search
	@references/cases/index-put.md	Batch load indices to UB, get_element reuse
MatMul	@references/cases/matmul-swizzle2d.md	Fixed core count grid, Swizzle2D block reordering
Reduction	@references/cases/reduction-amax-large.md	M≪N: reduce axis multi-core + atomic + secondary splitting
	@references/cases/reduction-amax-medium.md	Medium scale: matrix accumulation then reduction
	@references/cases/reduction-amax-small.md	Extremely small shape: grid=1 is optimal
	@references/cases/reduction-amin-atomic.md	Atomic amin: comparison of two atomic schemes
	@references/cases/reduction-amin-large.md	Very large 1D: secondary splitting + reorganization
	@references/cases/reduction-amin-medium.md	Large N-dimensional amin: matrix min then axis reduction
	@references/cases/reduction-amin-small.md	1D amin: parallelism balance
	@references/cases/reduction-mean-large.md	mean row secondary splitting
	@references/cases/reduction-mean-medium.md	mean reduce first axis: reorganization
	@references/cases/reduction-prod-small.md	prod: tl.reduce + custom mul
	@references/cases/reduction-sum-fused.md	elemwise + sum fusion
	@references/cases/reduction-sum-large.md	Large-scale sum: reorganization
	@references/cases/reduction-weighted-swiglu.md	3D SwiGLU backward: reshape + row secondary splitting

Knowledge loaded on demand

Condition	Load Document
The task description contains a hint marker (@hint:, @range_hint etc.)	@references/hint-mode.md

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Design Pattern

1. Carefully read the task_desc in Model.forward() 's reference implementation
2. Understand the operator's mathematical logic and computation pattern
3. Determine the operator type (elementwise / reduce / matmul / attention / composite)
4. Based on the target hardware architecture, select the appropriate parallelization strategy and memory access pattern
5. Use UnifiedSketch DSL to design the algorithm sketch

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Output Requirements

Directly output the algorithm sketch in sketch op_name { ... } format. If the task description contains a hint marker, append a "Design Applicability Scope" comment at the end of the sketch (format see hint-mode.md）。

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Design Principles

• Design aclear, understandablealgorithm flow
• Follow the best practices of Ascend NPU hardware characteristics (core-level parallelism, memory hierarchy)
• Consideroptimization opportunities of the target hardware architecture(parallelism, memory access patterns, data alignment)
• Annotateoptimization points and trade-off decisions(using @llm_hint annotations)
• Numerical correctness takes priority, performance comes second

Sketch Characteristics

The algorithm sketch should:

• High-level abstraction: Focus on algorithm logic and optimization strategies rather than implementation details
• Easy to understand: Convenient for triton-op-coding to convert into executable Triton Ascend code
• Include optimization hints: Annotate opportunities for parallelization, memory optimization, loop unrolling, etc.

Thinking Requirements

Important: During the thinking process, only perform framework-level analysis and decisions, for example:

• Operator type determination (elementwise / reduce / matmul, etc.)
• What parallel strategy to choose (core-level parallelism, data partitioning method)
• Tile size selection (considering NPU UB capacity and alignment requirements)
• How to handle data types

Do not write out the complete sketch during the thinking process; the complete sketch is only given in the final output.