Architecture generation overview
| Concept | Description |
|---|---|
| NpuArch | Chip architecture number, defines the instruction set and microarchitecture, obtained at runtime via GetCurNpuArch() 获取 |
| SocVersion | System-on-chip version, software naming identifier, obtained at runtime via GetSocVersion() 获取 |
| NPU_ARCH | Device-side compilation macro, four-digit numeric value, used for conditional compilation |
| archXX | Operator repository directory abbreviation, taking the first two digits of the DAV number (e.g., DAV_3510 → arch35) |
| DAV_C310 | Build system internal macro, equivalent to NpuArch::DAV_3510 / arch35 / __NPU_ARCH__=3510, cannot be inferred by numeric value |
Complete mapping table
For the complete product series / SocVersion / NpuArch / chip model mapping, see npu-hardware-params.md §0 Product mapping table。
Get current architecture
#include "utils/tiling/platform/platform_ascendc.h"
auto ascendcPlatform = platform_ascendc::PlatformAscendC(context->GetPlatformInfo());
NpuArch npuArch = ascendcPlatform.GetCurNpuArch(); // DAV_2201 / DAV_3510 / ...
platform_ascendc::SocVersion socVer = ascendcPlatform.GetSocVersion();
GetCurNpuArch() failure returns NpuArch::DAV_RESV，GetSocVersion() failure returns SocVersion::RESERVED_VERSION。
Key changes of DAV_3510 relative to DAV_2201
For the true values of detailed hardware parameters, see
references/npu-hardware-params.md. At runtime, the actual values must be obtained via thePlatformAscendCinterface; hardcoding is prohibited.
Buffer (usually consistent within the same architecture)
| Buffer | DAV_2201 | DAV_3510 |
|---|---|---|
| L0C | 128 KB | 256 KB |
| UB | 192 KB | 248 KB |
| BT | 1 KB | 4 KB |
Frequency/core count/L2/Memory (varies by model/form factor)
| Parameter | Ascend910B2 (DAV_2201) | Ascend950PR PCIE | Ascend950PR Server |
|---|---|---|---|
| Cube core count | 24 | 28 | 32 |
| Frequency | 1.8 GHz | 1.65 GHz | 1.65 GHz |
| L2 | 192 MB | 112 MB | 128 MB |
| Memory | 64 GB | 112 GB | 128 GB |
See Typical SKU examples。
Instruction set and microarchitecture
| Category | Change |
|---|---|
| Data format | Added FP8 / MXFP8 / MXFP4 / HiF8 Cube MMAD |
| CV direct path | Added L0C→UB, UB→L1, SSBuffer messages |
| Synchronization mechanism | BufferID replaces set/wait strict pairing |
| Programming model | Added SIMT, SIMD-Regbase, NDDMA, CCU compute-communication fusion |
Memory bandwidth is based on public information and empirical values, see
npu-hardware-params.md§4。
Detailed documentation index
references/ Load on demand:
npu-hardware-params.md— Hardware parameter reference: consistent parameters across sub-models of each architecture, typical SKU examples, specifications based on public information and empirical valuesnpu-arch-guide.md：- Typical hardware parameters and how to obtain them: typical values for core count / Buffer capacity,
GetCoreNumA*/GetCoreMemSize/aclrtGetDeviceInfointerface usage (including hardcoding counterexamples) - DAV_3510 microarchitecture: AI Core Buffer hierarchy, MTE engine, CV data path changes, BufferID synchronization
- SIMT vs SIMD: hardware capability differences and applicable scenarios
- SIMD-Regbase: register set, core advantages, code form changes
- Data format extension: complete data type table, C++ type name mapping, MXFP Tiling constraints
- NDDMA / CCU: high-dimensional DMA usage, three CCU communication paradigms, KFC scheduling model
- Architecture compatibility checklist / reference information sources
- Typical hardware parameters and how to obtain them: typical values for core count / Buffer capacity,
Scope boundaries: This skill focuses on architecture determination and hardware capability identification. Engineering template content such as operator directory structure, CMake configuration, and file naming conventions is outside the scope of this skill.